Fin field effect transistors (finFET) comprise a narrow source-channel-drain region (the fin) about which is formed a gate. Activation of the gate facilitates mobility of electron(s) or hole(s) in the channel between the source and the drain thereby facilitating operation of the finFET. An issue with finFET devices concerns controlling, from structures adjacent to the channel, diffusion of dopants and/or impurities, into the channel which accordingly affect electron/hole mobility in the channel and hence may deleteriously affect anticipated operation of the channel. For example, a high concentration of dopants/impurities in the channel can cause the channel threshold voltage (Vth) to drift away (i.e., increase or decrease) from an anticipated target Vth for the channel.
Further, to facilitate operation of a finFET device, the application of strain stressors to the gate/channel region may be desired to facilitate improved/controlled electron/hole mobility. However, owing to the placement of sidewalls on either side of the gate/channel it can be difficult to apply stressors that will generate the desired strain in the channel to facilitate the required level of electron/hole mobility.
With reference to FIG. 6, presented is a rudimentary depiction of a finFET device comprising a semiconductor substrate on which is formed a fin, around which is further formed a gate. As shown in FIG. 6, a semiconductor substrate (e.g., a Si-containing structure) 210 has formed thereon a fin 220, where the fin 220 has a source side (as indicated) and a drain side (not shown), with an isolating layer 240 further formed thereon. A gate 250 is formed over an isolating layer 240, with spacers 260 formed on the sidewalls of the gate 250, and an insulating layer 270 further formed thereon. Element isolating layer 240 can be deposited as part of a process associated with formation of fin 220, where in an aspect, element isolating layer 240 can comprise of any suitable material, such as a high aspect ratio process (HARP) oxide layer. As known in the art, the region of the fin 220 which is enclosed by gate 250 can act as a channel (not shown) between a source region and a drain region of the fin.
In a typical arrangement, as illustrated in FIG. 6, a doped epitaxial layer 290 can be formed in an attempt to generate strain in the gate 250 and isolating layer 240. The doped epitaxial layer 290 can comprise of silicon germanium compound (SiGe) or carbon-doped silicon (Si:C).
In another typical arrangement, as illustrated in FIGS. 7 and 8, to facilitate increasing the inducement of strain in the channel, the isolating layer (ref. with the element isolating layer 240 shown in FIG. 6) can be reduced such that it is confined to the region of the gate. As shown in FIGS. 7 and 8, fin(s) 320 are formed on substrate 310, with isolation region 340 and gate 350 formed thereon, with gate 350 being enclosed in spacer(s) 360 and insulating layer 370. By reducing the size of the isolating layer 340 so that it is confined to the region of the gate 350, is it possible to deposit doped epitaxial layer 390 to reside on increased areas (in comparison with the structure shown in FIG. 6) of fin(s) 320, and isolating layer 340 under gate 350. However, as shown in FIG. 8, such an approach can lead to deleterious effects such as junction leakage, junction capacitance, and off current pathways being encountered, owing to, for example, dopant migration from doped epitaxial layer 390 into substrate 310. To prevent such deleterious effects a buffer layer comprising dopant diffusion stopper is required.
Hence, another approach is to utilize a buffer layer between the substrate and the doped epitaxial layer. FIGS. 9 and 10a-c illustrate such an approach, where FIGS. 10a-c provide a view of a portion of the structure shown in FIG. 9, along direction X. As shown in FIG. 9, fin(s) 420 are formed on substrate 410, with isolation region 440 and gate 450 formed thereon, with gate 450 being enclosed in spacer(s) 460 and insulating layer 470. By reducing the size of the isolating layer 440 so that it is confined to the region of the gate 450, is it possible to deposit buffer epitaxial layer 495 to reside on fin(s) 420, and also to be located against isolating layer 440 under gate 450. However, as shown in FIGS. 9 and 10a-c, such an approach can lead to portions of buffer epitaxial layer 495 being deposited on to the upper surface E of fin(s) 420 which can impede the formation of doped epitaxial layer 490, as the doped epitaxial layer 490 is formed on the buffer epitaxial layer 495 located on the top of fin(s) 420.
In an aspect, the planer direction of the fin 420 is {001}, while stress from the buffer epitaxial layer 495 and the doped epitaxial layer 490 is in the {100} plane on the horizontal surfaces F and E and in the {110} plane on the vertical surfaces C and D. Hence, it is not possible to apply the {100} planar stress or the {110} planar stress on the fin in a truly combined manner to facilitate maximal stress (and according strain) being applied to the fin channel region, the stress transitions from being effectively 100% in the {110} plane and 0% in the {100} plane at the base of fin 420 through to being effectively 100% in the {100} plane and 0% in the {110} plane at the top surface E of fin 420. Thus, the stress throughout fin 420 is not of a consistent value or in a consistent direction.
Hence, as illustrated in FIGS. 6-10a-c, the ability to form an epitaxial layer such that the epitaxial layer provisions a desired degree of strain in any of the fin, channel, gate, or isolating layer can be difficult.